The present invention relates to a signal recognition system for reproducing a condition of an input signal as a condition of an output signal only when said input signal condition persists for at least a predetermined time interval, said system including a means for periodically scanning said input signal condition; a first memory means for storing a start value indicative of said time interval; a second memory means for storing a value indicative of the time already counted since the detection of a difference between said input and output signal conditions; a third memory means for storing the output signal condition; and a processing means for bringing said start value from said first memory means into said second memory means when no difference is detected and for modifying the value in said second memory means each time such a difference is detected and until a value is reached indicating that said time interval has been counted, said output signal condition in said third memory means being then changed.
Such a system is already known from the Belgian Pat. No. 880 921 (D. DE BAETS 1). In this known system the first memory means stores for each input signal condition a start value for the count down as well as a series of next values each decreased by one. These start and next values are successively brought in the second register means when a difference is detected between an input signal condition and an output signal condition and until the value stored in the second register means indicates that a required time interval had been counted, i.e. until the end of the count down has been reached. Hence, the first memory means is relatively large and each time a value stored in the second memory means has to be modified, the first memory means has to be accessed to obtain a next value. Moreover, for such an operation the real condition of the input signal has to be known since the next value is function of this condition.
An object of the present invention is to provide a signal recognition system of the above type, but which does not present these drawbacks.
According to the invention this object is achieved due to the fact that said first memory means only stores a single start value for all conditions of said input signal and that said processing means perform said modification in said second memory means indpendently of said first memory means.
Hence, the first memory means is relatively small and has not to be accessed each time the value stored in the said memory means has to be modified.
Another characteristic feature of the present system is that it includes an adder circuit whose sum output is coupled to an input of said second memory means, and an exclusive-OR gate which compares said input and output signal conditions and which when the result of this comparison indicates a difference couples an output of said second memory means to said adder circuit which then adds a 1 to the value stored in said second memory means.
Hence the modification of the value stored in the second memory means is performed by a simple adding operation and independently of the real condition of the input signal. The speed of such adding operation being relatively low, the present system may be integrated on a relatively small surface. Indeed, when for instance MOS technology is used wherein data transfer is realized by the charge and discharge of parasitic capacitances, a relatively low speed permits the use of transistors which provide relatively small currents to perform these charge and discharge operations and which may therefore be integrated on a relatively small surface.
The above mentioned and other objects and features of the invention will become more apparent and the invention itself will be best understood by referring to the following description of an embodiment taken in conjunction with the accompanying drawings in which: